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CANDY1
- 用VHDL实现的数字钟,实现消抖,计时,显示分秒,秒表等功能-VHDL implementation with digital clock and realize elimination shake, timing, displays minutes and seconds, stopwatch functions
VHDLshili
- 此内容为VHDL设计实例 一共有三个都是关于数字钟的功能要求的 但是没有说明 能看懂就行-The contents of VHDL design examples are a total of three functional requirements on the digital clock in but did not say can read on-line
digitclock
- 用vhdl实现的数字钟,具有整点报时,调时功能。-Implemented using vhdl digital clock, with the whole point timekeeping, transfer-time functionality.
shuzizhong_vhdl
- 用vhdl语言写的数字钟程序,有兴趣的可以-Vhdl language used to write the digital clock program, interested to see
exp5_clock
- VHDL语言编写的数字钟 具有清零、暂停、调整时间等功能-VHDL language of the digital clock has a clear, pause, adjust the time function
clock
- 数字钟 用VHDL 编写,内含QUARTUSII软件-digital clock
LIBRARY
- 基于VHDL的数字钟的设计,能够显示年月日,时分秒等功能。-VHDL-based digital clock designed to display years on, when minutes and seconds functions
VerilogHDL
- vhdl多功能数字钟数字钟是一种用数字电路技术实现时、分、秒计时的装置,与机械式时钟相比具有更高的准确性和直观性-vhdl multifunction digital clock digital clock is a digital circuit technology with the hours, minutes, seconds, timing devices, and mechanical clock higher than the accuracy and intuitive
VHDLdigitalclocktimer.
- 用VHDL语言编写的数字钟程序,可以实现计时功能,且具有整点报时功能,能够实现时、分、秒的十进制显示。-With VHDL language,it can realize the function of digital clock timer.
VHDL_clock
- VHDL数字钟设计程序 设计要求 基本要求: 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响);--VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (
clock
- 多功能数字钟,VHDL语言编写;是EDA学习中常见问题-CLOCK
DigitalClock
- 该数字钟,采用VHDL语言编写,具有即时,跑表,调时,调分,闹铃等功能,另外还可以增加一些功能,例如正点报时等-The digital clock, using VHDL language, with real-time, PaoBiao, adjustable, adjustable, alarm functions, also can add some functions, such as punctual
project
- 介绍了利用VHDL硬件描述语言设计的简易数字钟的思路和技巧。在QuatusⅡ开发环境中编译和仿真了所设计的程序,并在可编程逻辑器件上下载验证。仿真和验证结果表明,该设计方法切实可行,具有一定的借鉴性。-digital clock
Written_in_VHDL_Digital_Clock_Design
- VHDL语言编写的数字钟设计Digital Clock Design,电子系很经典的实验设计-Written in VHDL, Digital Clock Design Digital Clock Design, Department of Electronic Engineering is the classic experimental design
shuzizhong
- 基于VHDL的数字钟的设计,本文给出了详细的代码,直接可用!-VHDL-based digital clock design, this paper presents a detailed code, directly available!
clock
- 数字钟,用VHDL 编写。具有计时,校时(调分调时),报时功能-Digital clock, written with VHDL. With time, school time (when the tone on tones), timekeeping function
final
- 基于VHDL的数字钟实现,适用于大学数字电路与逻辑设计课程的期末考试或实验内容-VHDL-based digital clock implementation
shuzizhong_VHDL
- 用VHDL语言写了数字钟程序,并用数码管显示,经过硬件调试可行-timer clock
VHDLDigitalClock
- 数字钟的VHDL语言实现基本功能,包括 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响); -Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1
SHUZIZHONG
- 基于VHDL语言的数字钟的,包括显示,按键控制等-无